Many electronic devices typically operate according to specific requirements with regards to data output timing. For example, two timing parameters may be data access time and data hold time. Data access time is typically the maximum time from an external event (e.g., starting from an output of data from the device) until the data on the output of the device is valid. Data hold time is typically the minimum time data stays valid on data lines of a device after a new command to the device has been issued. These parameters are related to one another since they may be triggered by the same external event (e.g., they may be triggered by a read command received from an external device). Depending on the architecture, the brand, or the type of electronic device, the specific requirements for these timing parameters may be different.
To allow for maximum data-access rates, if several bits of data have to be output sequentially, each bit of data is usually driven until it is replaced by the next bit of data (i.e., with no invalid period between the data). If this is the case, data hold time may be equal to the minimum allowed access time (i.e., the hold time for the last bit of data) while the data access time may become the maximum allowed access time. Thus, devices may have a specification requirement for a minimum data hold time and a maximum data access time. Therefore, for proper operation with respect to the specification of the device, data output timing typically needs to fit within a window between data hold time and data access time. This window may be known as a data output timing window.
Factors such as manufacturing process variations, operating temperature variations and supply voltage variations may cause the propagation rate of signals passing through the device to change. Consequently, changes in the manufacturing process or changes in environmental variables may affect the data output timing such that the device no longer outputs data within the specified data output timing window (or “data eye”).
In response to data output timing requirements, some timing adjustment techniques have been devised. One solution to this problem has been to simulate an adjusted timing of the device in the design phase to meet the specification requirements. However, if the timing requirements are very narrow this solution may not be sufficient to compensate for variations in manufacturing yield or changes in environmental variables. Furthermore, the solution of adjustment of the timing during the design phase may be ineffective in devices that do not use voltage regulation. Voltage regulation may provide a constant voltage to an electronic device in response to changes in supply voltage and/or changes to temperature.
Other solutions are equally unsatisfactory. For example, some techniques may work well for device manufacturing process variations, but not for device voltage and temperature variations. Other solutions may use a free running clock, which increases power consumption of the device. In some cases, timing adjustment techniques may not be used for devices that operate in mixed modes (e.g., NOR-flash interface), asynchronously or that allow clock-suspended operation.